1. Field of the Invention
The invention relates generally to systems and methods for facilitating communication on a bus between master and slave devices. More particularly, the invention relates to systems and methods for facilitating the clearing of entries from a command buffer when transactions associated with the commands are canceled.
2. Related Art
Many of today's high-performance systems include multiple processors that share the computation load. In many multiple processor systems, some of the processors are set up as master devices and some of the processors are set up as slave devices. The master devices typically control the slave devices by sending data to and reading data from the slave devices through write and read commands. Communication between master and slave devices in such systems is typically accomplished with one or more busses. Busses have limited bandwidth that must be shared by all the devices on the bus, and thus, the implemented communication scheme over the busses should be as efficient as possible.
The transactions that are associated with each of the commands generated by a master device to facilitate data transfers typically require more than one phase or step to complete. For example, a write transaction requires the generation of a write command, a determination by the master device whether the slave device can accept the command, and the sending of data to be written to the slave device when the slave device indicates that it can accept the data. To increase the communication efficiency, multiple transactions may be in progress concurrently. That is, after a first command is generated by a master device and while execution of that command is still in progress, one or more additional commands may be generated by the master device or by other master devices.
A scheme is thus required to facilitate the association of the different phases of a transaction with each other since multiple transactions may be in progress concurrently. One such scheme involves the tagging of each communication with a tag that is unique-to each transaction. In a tagging scheme, after a command is generated by a master device, the command and a tag associated with the command are stored in a buffer. The tag is used to identify the command in the buffer until the transaction associated with the command is complete.
The tag is communicated with the command to the slave devices and the slave devices communicate the tag back to the master device with the replies sent to the master devices. When the master device receives a reply, the master device can determine the transaction with which the communication is associated by using the tag to identify the associated command in the buffer.
Because a master device assigns the tags to the commands in the buffer, the tags can be assigned in a way that minimizes the cost associated with using the tags to look up entries in the buffer. In particular, the tags can be assigned in such a way that they correspond to the physical locations of the corresponding commands in the buffer. For example, tag 1 may correspond to the first location in the buffer, and so on. The tags can then be used to index into the buffer rather than having to compare them to each of the tags in the buffer to determine the location of the corresponding command.
Slave devices can also use the tag generated by the master device as a way to associate phases of a transaction with each other. In the case of the slave devices, however, the tag is not an index into the buffer where information about the transactions in progress is stored. Slave devices can store the master tag and perhaps other information about the transactions in a buffer having a separate index. A content-addressable memory unit is thus typically required to associate incoming communications with previously received communications. A content-addressable memory unit can search through the contents in its memory to determine which, if any, of the entries stored in the memory (the previously received tags) match a specific value (the current tag). Content-addressable memory units require more time to retrieve an entry compared to a more traditional, indexed buffer since a search of the contents of the content-addressable memory unit is performed each time an entry is to be retrieved. In addition, content-addressable memory units require more logic than traditional buffers and thus require more physical space on an integrated circuit thereby increasing the cost of manufacturing.
Because of the cost associated with content-addressable memories, it would be desirable to provide a tag scheme that allows slave devices to more efficiently associate incoming communications with previously received communications.